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| 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A SST49LF002A / 003A / 004A / 008A2 Mb / 3 Mb / 4 Mb / 8 Mb Firmware Hub for Intel 8xx Chipsets www..com Advance Information FEATURES: * Firmware Hub for Intel 8xx Chipsets * 2 Mbit, 3 Mbit, 4 Mbit, or 8 Mbit SuperFlash memory array for code/data storage - SST49LF002A: 256K x8 (2 Mbit) - SST49LF003A: 384K x8 (3 Mbit) - SST49LF004A: 512K x8 (4 Mbit) - SST49LF008A: 1024K x8 (8 Mbit) * Flexible Erase Capability - Uniform 4 KByte Sectors - Uniform 16 KByte overlay blocks for SST49LF002A - Uniform 64 KByte overlay blocks for SST49LF003A/004A/008A - Top Boot Block protection - 16 KByte for SST49LF002A - 64 KByte for SST49LF003A/004A/008A - Chip-Erase for PP Mode Only * Single 3.0-3.6V Read and Write Operations * Superior Reliability - Endurance:100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption - Active Read Current: 6 mA (typical) - Standby Current: 10 A (typical) * Fast Sector-Erase/Byte-Program Operation - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 70 ms (typical) - Byte-Program Time: 14 s (typical) - Chip Rewrite Time: SST49LF002A: 4 seconds (typical) SST49LF003A: 6 seconds (typical) SST49LF004A: 8 seconds (typical) SST49LF008A: 15 seconds (typical) - Single-pulse Program or Erase - Internal timing generation * Two Operational Modes - Firmware Hub Interface (FWH) Mode for in-system operation - Parallel Programming (PP) Mode for fast production programming * Firmware Hub Hardware Interface Mode - 5-signal communication interface supporting byte Read and Write - 33 MHz clock frequency operation - WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block - Block Locking Register for all blocks - Standard SDP Command Set - Data# Polling and Toggle Bit for End-of-Write detection - 5 GPI pins for system design flexibility - 4 ID pins for multi-chip selection * Parallel Programming (PP) Mode - 11-pin multiplexed address and 8-pin data I/O interface - Supports fast In-System or PROM programming for manufacturing * CMOS and PCI I/O Compatibility * Packages Available - 32-lead PLCC - 32-lead TSOP (8mm x 14mm) PRODUCT DESCRIPTION The SST49LF00xA flash memory devices are designed to be read-compatible with the Intel 82802 Firmware Hub (FWH) device for PC-BIOS application. It provides protection for the storage and update of code and data in addition to adding system design flexibility through five general purpose inputs. Two interface modes are supported by the SST49LF00xA: Firmware Hub (FWH) Interface Mode for In-System programming and Parallel Programming (PP) Mode for fast factory programming of PC-BIOS applications. The SST49LF00xA flash memory devices are manufactured with SST's proprietary, high performance SuperFlash Technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST49LF00xA devices significantly improve performance and reliability, while lowering power consumption. The SST49LF00xA devices write (Program or Erase) with a single 3.0-3.6V power supply. It uses less energy during Erase and Program than alternative flash memory technologies. The total energy consumed is a function of the applied voltage, current and time of application. Since for (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation. These specifications are subject to change without notice. 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST49LF00xA products provide a maximum ByteProgram time of 20 sec. The entire memory can be erased and programmed byte-by-byte typically in 15 seconds for an 8-Mbit device, when using status detection features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. The SuperFlash technology provides fixed Erase and Program time, independent of the number of Erase/Program cycles that have performed. Therefore the system software or hardware does not have to be calibrated or correlated to the cumulated number of Erase/Program cycles as is necessary with alternative flash memory technologies, whose Erase and Program time increase with accumulated Erase/Program cycles. To protect against inadvertent write, the SST49LF00xA devices employ hardware and software data (SDP) protection schemes. It is offered with typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. To meet high density, surface mount requirements, the SST49LF00xA device is offered in 32-lead TSOP and 32lead PLCC packages. See Figures 7 and 8 for pinouts and Table 8 for pin descriptions. nication between Host and the SST49LF00xA occurs via the 4-bit I/O communication signals, FWH [3:0] and the FWH4. In PP mode, the device is programmed via an 11bit address and an 8-bit data I/O parallel signals. The address inputs are multiplexed in row and column selected by control signal R/C# pin. The column addresses are mapped to the higher internal addresses, and the row addresses are mapped to the lower internal addresses. See the Device Memory Maps in Figures 3 through 6 for address assignments. www..com FIRMWARE HUB (FWH) MODE Device Operation The FWH mode uses a 5-signal communication interface, FWH[3:0] and FWH4, to control operations of the SST49LF00xA. Operations such as Memory Read and Memory Write uses Intel FWH propriety protocol. JEDEC Standard SDP (Software Data Protection) Byte-Program, Sector-Erase and Block-Erase command sequences are incorporated into the FWH memory cycles. Chip-Erase is only available in PP Mode. The device enters standby mode when FWH4 is high and no internal operation is in progress. The device is in ready mode when FWH4 is low and no activity is on the FWH bus. Firmware Hub Interface Cycles Addresses and data are transferred to and from the SST49LF00xA by a series of "fields," where each field contains 4 bits of data. ST49LF00xA supports only single-byte read and writes, and all fields are one clock cycle in length. Field sequences and contents are strictly defined for Read and Write operations. Addresses in this section refer to addresses as seen from the SST49LF00xA's "point of view," some calculation will be required to translate these to the actual locations in the memory map (and vice versa) if multiple memory device is used on the bus. Tables 1 and 2 list the field sequences for Read and Write cycles. Mode Selection and Description The SST49LF00xA flash memory devices can operate in two distinct interface modes: the Firmware Hub Interface (FWH) mode and the Parallel Programming (PP) mode. The IC (Interface Configuration pin) is used to set the interface mode selection. If the IC pin is set to logic High, the device is in PP mode; while if the IC pin is set Low, the device is in the FWH mode. The IC selection pin must be configured prior to device operation. The IC pin is internally pulled down if the pin is not connected. In FWH mode, the device is configured to interface with its host using Intel's Firmware Hub proprietary protocol. Commu- (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 2 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information TABLE 1: FWH READ CYCLE Clock Cycle 1 Field Name START Field Contents FWH[3:0]1 1101 FWH[3:0] Direction IN Comments www..com FWH4 must be active (low) for the part to respond. Only the last start field (before FWH4 transitioning high) should be recognized. The START field contents indicate a FWH memory read cycle. Indicates which FWH device should respond. If the to IDSEL (ID select) field matches the value ID[3:0], then that particular device will respond to the whole bus cycle. These seven clock cycles make up the 28-bit memory address. YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first. A field of this size indicates how many bytes will be or transferred during multi-byte operations. The SST49LF00xA will only support single-byte operation. IMSIZE=0000b In this clock cycle, the master (Intel ICH) has driven the bus then float to all `1's and then floats the bus, prior to the next clock cycle. This is the first part of the bus "turnaround cycle." The SST49LF00xA takes control of the bus during this cycle. During the next clock cycle, it will be driving "sync data." During this clock cycle, the FWH will generate a "readysync" (RSYNC) indicating that the least-significant nibble of the least-significant byte will be available during the next clock cycle. YYYY is the least-significant nibble of the least-significant data byte. YYYY is the most-significant nibble of the least-significant data byte. In this clock cycle, the SST49LF00xA has driven the bus to all ones and then floats the bus prior to the next clock cycle. This is the first part of the bus "turnaround cycle." The master (Intel ICH) resumes control of the bus during this cycle. T1.3 504 2 IDSEL 0000 to 1111 IN 3-9 IMADDR YYYY IN 10 IMSIZE 0000 (1 byte) IN 11 TAR0 1111 IN then Float 12 TAR1 1111 (float) Float then OUT OUT 13 RSYNC 0000 (READY) 14 15 16 DATA DATA TAR0 YYYY YYYY 1111 OUT OUT OUT then Float Float then IN 17 TAR1 1111 (float) 1. Field contents are valid on the rising edge of the present clock cycle. CLK FWH4 FWH[3:0] STR IDS IMADDR IMS TAR RSYNC DATA TAR 504 ILL F59.1 FIGURE 1: SINGLE-BYTE READ WAVEFORMS (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 3 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information TABLE 2: FWH WRITE CYCLE Clock Cycle 1 Field Name START Field Contents FWH[3:0]1 1110 FWH[3:0] Direction IN Comments FWH4 must be active (low) for the part to respond. Only the last start field (before FWH4 transitioning high) should be recognized. The START field contents indicate a FWH memory read cycle. Indicates which SST49LF00xA device should respond. If the IDSEL (ID select) field matches the value ID[3:0], then that particular device will respond to the whole bus cycle. These seven clock cycles make up the 28-bit memory address. YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first. This size field indicates how many bytes will be transferred during multi-byte operations. The FWH only supports single-byte writes. IMSIZE=0000b This field is the least-significant nibble of the data byte. This data is either the data to be programmed into the flash memory or any valid flash command. This field is the most-significant nibble of the data byte. In this clock cycle, the master (Intel ICH) has driven the then float bus to all `1's and then floats the bus prior to the next clock cycle. This is the first part of the bus "turnaround cycle." The SST49LF00xA takes control of the bus during this cycle. During the next clock cycle it will be driving the "sync" data. The SST49LF00xA outputs the values 0000, indicating that it has received data or a flash command. In this clock cycle, the SST49LF00xA has driven the bus to all then float `1's and then floats the bus prior to the next clock cycle. This is the first part of the bus "turnaround cycle." The master (Intel ICH) resumes control of the bus during this cycle. T2.4 504 www..com 2 IDSEL 0000 to 1111 IN 3-9 IMADDR YYYY IN 10 IMSIZE 0000 (1 byte) IN 11 DATA YYYY IN 12 13 DATA TAR0 YYYY 1111 IN IN then Float 14 TAR1 1111 (float) Float then OUT 15 16 RSYNC TAR0 0000 1111 OUT OUT then Float 17 TAR1 1111 (float) Float then IN 1. Field contents are valid on the rising edge of the present clock cycle. CLK FWH4 FWH[3:0] STR IDS IMADDR IMS DATA TAR RSYNC TAR 504 ILL F60.1 FIGURE 2: WRITE WAVEFORMS (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 4 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com Abort Mechanism If FWH4 is driven low for one or more clock cycles during a FWH cycle, the cycle will be terminated and the device will wait for the ABORT command. The host must drive the FWH[3:0] with `1111b' (ABORT command) to return the device to ready mode. If abort occurs during the internal write cycle, the data may be incorrectly programmed or erased. It is required to wait for the Write operation to complete prior to initiation of the abort command. It is recommended to check the Write status with Data# Polling (DQ7) or Toggle Bit (DQ6) pins. One other option is to wait for the fixed write time to expire. flash memory address range for the SST49LF003A/ 004A/008A and 4 boot sectors (16 KByte) for SST49LF002A. WP# pin write protects the remaining sectors in the flash memory. An active low signal at the TBL# pin prevents Program and Erase operations of the top boot sectors. When TBL# pin is held high, write protection of the top boot sectors is then determined by the Boot Block Locking register. The WP# pin serves the same function for the remaining sectors of the device memory. The TBL# and WP# pins write protection functions operate independently of one another. Both TBL# and WP# pins must be set to their required protection states prior to starting a Program or Erase operation. A logic level change occurring at the TBL# or WP# pin during a Program or Erase operation could cause unpredictable results. TBL# and WP# pins cannot be left unconnected. TBL# is internally ORed with the top Boot Block Locking register. When TBL# is low, the top Boot Block is hardware write protected regardless of the state of the WriteLock bit for the Boot Block Locking register. Clearing the Write-Protect bit in the register when TBL# is low will have no functional effect, even though the register may indicate that the block is no longer locked. WP# is internally ORed with the Block Locking register. When WP# is low, the blocks are hardware write protected regardless of the state of the Write-Lock bit for the corresponding Block Locking registers. Clearing the Write-Protect bit in any register when WP# is low will have no functional effect, even though the register may indicate that the block is no longer locked. Response To Invalid Fields During FWH operations, the FWH will not explicitly indicate that it has received invalid field sequences. The response to specific invalid fields or sequences is as follows: Address out of range: The FWH address sequence is 7 fields long (28 bits), but only the last five address fields (20 bits) will be decoded by SST49LF00xA. Address A22 has the special function of directing reads and writes to the flash core (A22=1) or to the register space (A22=0). The SST49LF003A features are equivalent to the SST49LF004A with 128 KByte less memory. For the SST49LF003A, operations beyond the 3-Mbit boundary (below 20000H) are not valid (see Device Memory Map). Invalid address range locations will read as 00H. Invalid IMSIZE field: If the FWH receives an invalid size field during a Read or Write operation, the device will reset and no operation will be attempted. The SST49LF00xA will not generate any kind of response in this situation. Invalidsize fields for a Read/Write cycle are anything but 0000b. Once valid START, IDSEL, and IMSIZE fields are received, the SST49LF00xA always will respond to subsequent inputs as if they were valid. As long as the states of device FWH[3:0] and FWH4 are known, the response of the SST49LF00xA to signals received during the FWH cycle should be predictable. The SST49LF00xA will make no attempt to check the validity of incoming flash operation commands. Reset A VIL on INIT# or RST# pin initiates a device reset. INIT# and RST# pins have the same function internally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper CPU initialization. During a Read operation, driving INIT# or RST# pins low deselects the device and places the output drivers, FWH[3:0], in a high-impedance state. The reset signal must be held low for a minimal duration of time TRSTP. A reset latency will occur if a reset procedure is performed during a Program or Erase operation. See Table 18, Reset Timing Parameters for more information. A device reset during an active Program or Erase will abort the operation and memory contents may become invalid due to data being altered or corrupted from an incomplete Erase or Program operation. Device Memory Hardware Write Protection The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of device memory in the SST49LF00xA. The TBL# pin is used to write protect 16 boot sectors (64 KByte) at the highest (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 5 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com Write Operation Status Detection The SST49LF00xA device provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is incorporated into the FWH Read Cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Controller Hub documentation. Since there is no ID support in PP Mode, to program multiple devices a stand-alone PROM programmer is recommended. REGISTERS There are three types of registers available on the SST49LF00xA, the General Purpose Inputs Register, Block Locking Registers and the JEDEC ID Registers. These registers appear at their respective address location in the 4 GByte system memory map. Unused register locations will read as 00H. Any attempt to read or write any registers during internal Write operation will be ignored. General Purpose Inputs Register The GPI_REG (General Purpose Inputs Register) passes the state of FGPI[4:0] pins at power-up on the SST49LF00xA. It is recommended that the FGPI[4:0] pins are in the desired state before FWH4 is brought low for the beginning of the bus cycle, and remain in that state until the end of the cycle. There is no default value since this is a pass-through register. The GPI register for the boot device appears at FFBC0100H in the 4 GByte system memory map, and will appear elsewhere if the device is not the boot device. Register is not available for read when the device is in Erase/Program operation. See Table 3 for the GPI_REG bits and function. TABLE 3: GENERAL PURPOSE INPUTS REGISTER Pin # Bit 7:5 4 Function Reserved FGPI[4] Reads status of general purpose input pin FGPI[3] Reads status of general purpose input pin FGPI[2] Reads status of general purpose input pin FGPI[1] Reads status of general purpose input pin FGPI[0] Reads status of general purpose input pin 32-PLCC 30 32-TSOP 6 Data# Polling (DQ7) When the SST49LF00xA device is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. Proper status will not be given using Data# Polling if the address is in the invalid range. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating `0's and `1's, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. 3 3 11 2 4 12 Multiple Device Selection The four ID pins, ID[3:0], allow multiple devices to be attached to the same bus by using different ID strapping in a system. When the SST49LF00xA is used as a boot device, ID[3:0] must be strapped as 0000, all subsequent devices should use a sequential up-count strapping (i.e. 0001, 0010, 0011, etc.). The SST49LF00xA will compare the strapping values, if there is a mismatch, the device will ignore the remainder of the cycle and go into standby mode. For further information regarding FWH device mapping and paging, please refer to the Intel 82801(ICH) I/O (c)2001 Silicon Storage Technology, Inc. 1 5 13 0 6 14 T3.2 504 S71161-06-000 9/01 504 6 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com Block Locking Registers SST49LF00xA provides software controlled lock protection through a set of Block Locking registers. The Block Locking Registers are read/write registers and it is accessible through standard addressable memory locations specified in Table 4 and Table 5. Unused register locations will read as 00H. TABLE 4: BLOCK LOCKING REGISTERS FOR SST49LF002A1 Register T_BLOCK_LK T_MINUS01_LK Block Size 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K Protected Memory Address Package 3FFFFH - 3C000H 3BFFFH - 38000H 37FFFH - 34000H 33FFFH - 30000H 2FFFFH - 2C000H 2BFFFH - 28000H 27FFFH - 24000H 23FFFH - 20000H 1FFFFH - 1C000H 1BFFFH - 18000H 17FFFH - 14000H 13FFFH - 10000H 0FFFFH - 0C000H 0BFFFH - 08000H 07FFFH - 04000H 03FFFH - 00000H Memory Map Register Address FFBF8002H FFBF0002H T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK FFBE8002H FFBE0002H FFBD8002H FFBD0002H FFBC8002H FFBC0002H T4.1 504 1. Default value at power up is 01H TABLE 5: BLOCK LOCKING REGISTERS FOR SST49LF003A/004A/008A1 Register T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK T_MINUS08_LK T_MINUS09_LK T_MINUS10_LK T_MINUS11_LK T_MINUS12_LK T_MINUS13_LK T_MINUS14_LK T_MINUS15_LK Block Size 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K Protected Memory Address Range SST49LF003A 07FFFFH - 070000H 06FFFFH - 060000H 05FFFFH - 050000H 04FFFFH - 040000H 03FFFFH - 030000H 02FFFFH - 020000H SST49LF004A 07FFFFH - 070000H 06FFFFH - 060000H 05FFFFH - 050000H 04FFFFH - 040000H 03FFFFH - 030000H 02FFFFH - 020000H 01FFFFH - 010000H 00FFFFH - 000000H SST49LF008A 0FFFFFH - 0F0000H 0EFFFFH - 0E0000H 0DFFFFH - 0D0000H 0CFFFFH - 0C0000H 0BFFFFH - 0B0000H 0AFFFFH - 0A0000H 09FFFFH - 090000H 08FFFFH - 080000H 07FFFFH - 070000H 06FFFFH - 060000H 05FFFFH - 050000H 04FFFFH - 040000H 03FFFFH - 030000H 02FFFFH - 020000H 01FFFFH -010000H 00FFFFH - 000000H Memory Map Register Address FFBF0002H FFBE0002H FFBD0002H FFBC0002H FFBB0002H FFBA0002H FFB90002H FFB80002H FFB70002H FFB60002H FFB50002H FFB40002H FFB30002H FFB20002H FFB10002H FFB00002H T5.2 504 1. Default value at power up is 01H (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 7 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information TABLE 6: BLOCK LOCKING REGISTER BITS Reserved Bit [7..2] 000000 000000 000000 000000 Lock-Down Bit [1] 0 0 1 1 Write-Lock Bit [0] 0 1 0 1 Lock Status Full Access Write Locked (Default State at Power-Up) Locked Open (Full Access Locked Down) Write Locked Down T6.3 504 www..com Write Lock The Write-Lock bit, bit 0, controls the lock state described in Table 6. The default Write status of all blocks after powerup is write locked. When bit 0 of the Block Locking register is set, Program and Erase operations for the corresponding block are prevented. Clearing the Write-Lock bit will unprotect the block. The Write-Lock bit must be cleared prior to starting a Program or Erase operation since it is sampled at the beginning of the operation. The Write-Lock bit functions in conjunction with the hardware Write Lock pin TBL# for the top Boot Block. When TBL# is low, it overrides the software locking scheme. The top Boot Block Locking register does not indicate the state of the TBL# pin. The Write-Lock bit functions in conjunction with the hardware WP# pin for blocks 0 to 6. When WP# is low, it overrides the software locking scheme. The Block Locking register does not indicate the state of the WP# pin. PARALLEL PROGRAMMING MODE Device Operation Commands are used to initiate the memory operation functions of the device. The data portion of the software command sequence is latched on the rising edge of WE#. During the software command sequence the row address is latched on the falling edge of R/C# and the column address is latched on the rising edge of R/C#. Read The Read operation of the SST49LF00xA device is controlled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle timing diagram, Figure 14, for further details. Reset A VIL on RST# pin initiates a device reset. Lock Down The Lock-Down bit, bit 1, controls the Block Locking register as described in Table 6. When in the FWH interface mode, the default Lock Down status of all blocks upon power-up is not locked down. Once the Lock-Down bit is set, any future attempted changes to that Block Locking register will be ignored. The Lock-Down bit is only cleared upon a device reset with RST# or INIT# or power down. Current Lock Down status of a particular block can be determined by reading the corresponding Lock-Down bit. Once a block's Lock-Down bit is set, the Write-Lock bits for that block can no longer be modified, and the block is locked down in its current state of write accessibility. Byte-Program Operation The SST49LF00xA device is programmed on a byte-bybyte basis. Before programming, one must ensure that the sector, in which the byte which is being programmed exists, is fully erased. The Byte-Program operation is initiated by executing a four-byte command load sequence for Software Data Protection with address (BA) and data in the last byte sequence. During the Byte-Program operation, the row address (A10-A0) is latched on the falling edge of R/C# and the column Address (A21-A11) is latched on the rising edge of R/C#. The data bus is latched in the rising edge of WE#. The Program operation, once initiated, will be completed, within 20 s. See Figure 15 for Program operation timing diagram, Figure 18 for timing waveforms, and Figure 26 for its flowchart. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. JEDEC ID Registers The JEDEC ID registers for the boot device appear at FFBC0000H and FFBC0001H in the 4 GByte system memory map, and will appear elsewhere if the device is not the boot device. Register is not available for read when the device is in Erase/Program operation. Unused register location will read as 00H. Refer to the relevant application note for details. See Table 7 for the device ID code. (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 8 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The SectorErase operation is initiated by executing a six-byte command load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 19 for Sector-Erase timing waveforms. Any commands written during the Sector-Erase operation will be ignored. Write Operation Status Detection The SST49LF00xA device provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Block-Erase Operation The Block-Erase Operation allows the system to erase the device in 64 KByte uniform block size for the SST49LF003A/SST49LF004A/SST49LF008A and 16 KByte uniform block size for the SST49LF002A. The Block-Erase operation is initiated by executing a six-byte command load sequence for Software Data Protection with Block-Erase command (50H) and block address. The internal Block-Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 20 for timing waveforms. Any commands written during the Block-Erase operation will be ignored. Data# Polling (DQ7) When the SST49LF00xA device is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# pulse for Program operation. For Sector- or ChipErase, the Data# Polling is valid after the rising edge of sixth WE# pulse. See Figure 16 for Data# Polling timing diagram and Figure 27 for a flowchart. Proper status will not be given using Data# Polling if the address is in the invalid range. Chip-Erase The SST49LF00xA device provides a Chip-Erase operation only in PP Mode, which allows the user to erase the entire memory array to the `1's state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE#. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 10 for the command sequence, Figure 21 for timing diagram, and Figure 29 for the flowchart. Any commands written during the Chip-Erase operation will be ignored. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating `0's and `1's, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# pulse. See Figure 17 for Toggle Bit timing diagram and Figure 27 for a flowchart. (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 9 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com Data Protection The SST49LF00xA device provides both hardware and software features to protect nonvolatile data from inadvertent writes. Product Identification The product identification mode identifies the device as the SST49LF00xA and manufacturer as SST. TABLE 7: PRODUCT IDENTIFICATION Hardware Data Protection Noise/Glitch Protection: A WE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Manufacturer's ID Device ID SST49LF002A SST49LF003A SST49LF004A SST49LF008A 0001H 0001H 0001H 0001H 57H 1BH 60H 5AH Byte 0000H Data BFH JEDEC ID Address Location FFBC0000H FFBC0001H FFBC0001H FFBC0001H FFBC0001H T7.5 504 Software Data Protection (SDP) The SST49LF00xA provides the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., program and erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six byte load sequence. The SST49LF00xA device is shipped with the Software Data Protection permanently enabled. See Table 10 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC. Design Considerations SST recommends a high frequency 0.1 F ceramic capacitor to be placed as close as possible between VDD and VSS less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 F electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. If you use a socket for programming purposes add an additional 1-10 F next to each socket. The RST# pin must remain stable at VIH for the entire duration of an Erase operation. WP# must remain stable at VIH for the entire duration of the Erase and Program operations for non-Boot Block sectors. To write data to the top Boot Block sectors, the TBL# pin must also remain stable at VIH for the entire duration of the Erase and Program operations. Electrical Specifications The AC and DC specifications for the FWH Interface signals (FWH[3:0], CLK, FWH4, and RST#) as defined in Section 4.2.2 of the PCI Local Bus Specification, Rev. 2.1. Refer to Table 11 for the DC voltage and current specifications. Refer to the tables on pages 20 through 24 for the AC timing specifications for Clock, Read/Write, and Reset operations. (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 10 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com System Memory (Top 4 MByte) FFFFFFFFH SST49LF002A (2 Mbit) SST49LF003A (3 Mbit) FFFC0000H SST49LF004A (4 Mbit) SST49LF008A (8 Mbit) FFFA0000H FFF80000H FFF00000H Range for Additional FWH Devices FFC00000H 504 ILL B1A.3 BOOT-CONFIGURATION SYSTEM MEMORY MAP (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 11 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com FUNCTIONAL BLOCK DIAGRAM TBL# WP# INIT# X-Decoder FWH[3:0] CLK FWH4 ID[3:0] FGPI[4:0] R/C# A[10:0] DQ[7:0] OE# WE# SuperFlash Memory FWH Interface Address Buffers & Latches Y-Decoder Control Logic I/O Buffers and Data Latches Programmer Interface IC RST# 504 ILL B1.2 (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 12 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com TBL# Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 3FFFFH Boot Block 3C000H 3BFFFH 38000H 37FFFH 34000H 33FFFH 30000H 2FFFFH 2C000H 2BFFFH 28000H 27FFFH 24000H 23FFFH WP# for Block 0~14 20000H 1FFFFH Block 7 1C000H 1BFFFH Block 6 18000H 17FFFH Block 5 14000H 13FFFH Block 4 10000H 0FFFFH Block 3 0C000H 0BFFFH Block 2 Block 1 08000H 07FFFH 04000H 03FFFH 300000 02FFFH 02000H 01FFFH 01000H 00FFFH 00000H 4 KByte Sector 3 4 KByte Sector 2 4 KByte Sector 1 4 KByte Sector 0 504 ILL F52.7 Block 0 (16 KByte) FIGURE 3: DEVICE MEMORY MAP FOR SST49LF002A (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 13 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com 7FFFFH TBL# Block 7 70000H 6FFFFH Block 6 60000H 5FFFFH Block 5 Boot Block WP# for Block 2~6 50000H 4FFFFH Block 4 40000H 3FFFFH Block 3 30000H 2F000H Block 2 22000H 21000H 20000H 1FFFFH 10000H 0FFFFH Invalid Range 4 KByte Sector 47 4 KByte Sector 34 4 KByte Sector 33 4 KByte Sector 32 Invalid Range *Block 1 *Block 0 (64 KByte) * operations to shaded area are not valid. 00000H 504 ILL F56.1 FIGURE 4: DEVICE MEMORY MAP FOR SST49LF003A 7FFFFH TBL# Block 7 70000H 6FFFFH Block 6 60000H 5FFFFH Block 5 50000H 4FFFFH Block 4 40000H 3FFFFH Block 3 30000H 2FFFFH Block 2 20000H 1FFFFH Block 1 10000H 0F000H Block 0 (64 KByte) 02000H 01000H 00000H Boot Block WP# for Block 0~6 4 KByte Sector 2 4 KByte Sector 1 4 KByte Sector 0 504 ILL F45.5 FIGURE 5: DEVICE MEMORY MAP (c)2001 Silicon Storage Technology, Inc. FOR SST49LF004A S71161-06-000 9/01 504 14 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com TBL# Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 0FFFFFH Boot Block 0F0000H 0EFFFFH 0E0000H 0DFFFFH 0D0000H 0CFFFFH 0C0000H 0BFFFFH 0B0000H 0AFFFFH 0A0000H 09FFFFH 090000H 08FFFFH WP# for Block 0~14 080000H 07FFFFH Block 7 070000H 06FFFFH Block 6 060000H 05FFFFH Block 5 050000H 04FFFFH Block 4 040000H 03FFFFH Block 3 030000H 02FFFFH Block 2 Block 1 020000H 01FFFFH 010000H 00FFFFH Block 0 (64 KByte) 002000H 001000H 000000H 4 KByte Sector 15 4 KByte Sector 2 4 KByte Sector 1 4 KByte Sector 0 504 ILL F57.0 FIGURE 6: DEVICE MEMORY MAP FOR SST49LF008A (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 15 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com NC NC NC VSS (VSS) IC (IC) A10 (FGPI4) R/C# (CLK) VDD (VDD) NC RST# (RST#) A9 (FGPI3) A8 (FGPI2) A7 (FGPI1) A6 (FGPI0) A5 (WP#) A4 (TBL#) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Standard Pinout Top View Die Up 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# (INIT#) WE# (FWH4) VDD (VDD) DQ7 (RES) DQ6 (RES) DQ5 (RES) DQ4 (RES) DQ3 (FWH3) VSS (VSS) DQ2 (FWH2) DQ1 (FWH1) DQ0 (FWH0) A0 (ID0) A1 (ID1) A2 (ID2) A3 (ID3) 504 ILL F01.4 ( ) Designates FWH Mode FIGURE 7: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM) RST# (RST#) A7(FGPI1) A6 (FGPI0) A5 (WP#) A4 (TBL#) A3 (ID3) A2 (ID2) A1 (ID1) A0 (ID0) DQ0 (FWH0) 5 6 7 8 9 10 11 12 13 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 VDD (VDD) A8 (FGPI2) A9 (FGPI3) NC A10 (FGPI4) R/C# (CLK) IC (IC) VSS (VSS) NC NC VDD (VDD) OE# (INIT#) WE# (FWH4) NC DQ7 (RES) 32-lead PLCC Top View 21 14 15 16 17 18 19 20 DQ3 (FWH3) DQ4 (RES) DQ5 (RES) DQ1 (FWH1) DQ2 (FWH2) DQ6 (RES) VSS (VSS) 504 ILL F02.3 ( ) Designates FWH Mode FIGURE 8: PIN ASSIGNMENTS FOR 32-LEAD PLCC (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 16 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information TABLE 8: PIN DESCRIPTION Interface Symbol A10-A0 Pin Name Address Type1 I PP X FWH Functions www..com Inputs for low-order addresses during Read and Write operations. Addresses are internally latched during a Write cycle. For the programming interface, these addresses are latched by R/C# and share the same pins as the high-order address inputs. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# is high. To gate the data output buffers To control the Write operations X This pin determines which interface is operational. When held high, programmer mode is enabled and when held low, FWH mode is enabled. This pin must be setup at power-up or before return from reset and not change during device operation. This pin is internally pulled- down with a resistor between 20-100 K. This is the second reset pin for in-system use. This pin is internally combined with the RST# pin; If this pin or RST# pin is driven low, identical operation is exhibited. These four pins are part of the mechanism that allows multiple parts to be attached to the same bus. The strapping of these pins is used to identify the component.The boot device must have ID[3:0]=0000 and it is recommended that all subsequent devices should use sequential up-count strapping. These pins are internally pulled-down with a resistor between 20-100 K. These individual inputs can be used for additional board flexibility. The state of these pins can be read through GPI_REG register. These inputs should be at their desired state before the start of the PCI clock cycle during which the read is attempted, and should remain in place until the end of the Read cycle. Unused GPI pins must not be floated. When low, prevents programming to the Boot Block sectors at top of memory. When TBL# is high it disables hardware write protection for the top block sectors. This pin cannot be left unconnected. I/O Communications To provide a clock input to the control unit Input Communications To reset the operation of the device When low, prevents programming to all but the highest addressable blocks. When WP# is high it disables hardware write protection for these blocks. This pin cannot be left unconnected. Select For the Programming interface, this pin determines whether the address pins are pointing to the row addresses, or to the column addresses. X These pins must be left unconnected. To provide power supply (3.0-3.6V) Circuit ground (OV reference) Every VSS pin must be grounded. Unconnected pins T8.3 504 DQ7-DQ0 Data I/O X OE# WE# IC Output Enable Write Enable Interface Configuration Pin I I I X X X INIT# Initialize I X ID[3:0] Identification Inputs I X FGPI[4:0] General Purpose Inputs I X TBL# Top Block Lock I X FWH[3:0] FWH I/Os CLK FWH4 RST# WP# Clock FWH Input Reset Write Protect I/O I I I I X X X X X X R/C# Row/Column Select I X RES VDD VSS NC Reserved Power Supply Ground No Connection I I I X X X X X X 1. I = Input, O = Output (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 17 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information TABLE 9: OPERATION MODES SELECTION (PP MODE) Mode Read Program Erase Reset Write Inhibit Product Identification RST# OE# VIL WE# DQ DOUT DIN X1 High Z High Z/DOUT High Z/DOUT Manufacturer's ID (BFH) Device ID2 Address AIN AIN Sector or Block address, XXH for Chip-Erase X X X A18-A1=VIL, A0=VIL A18-A1=VIL, A0=VIH T9.4 504 www..com VIH VIH VIH VIL VIH VIL VIL X X VIH VIH X VIL VIH X VIH VIL VIH VIH 1. X can be VIL or VIH, but no other value. 2. Device ID 57H for SST49LF002A, 1BH for SST49LF003A, 60H for SST49LF004A, and 5AH for SST49LF008A TABLE 10: SOFTWARE COMMAND SEQUENCE Command Sequence Byte-Program Sector-Erase Block-Erase Chip-Erase6 Software ID Entry7,8 Software ID Exit9 Software ID Exit9 1st1 Write Cycle Addr2 5555H 5555H 5555H 5555H 5555H XXH 5555H Data AAH AAH AAH AAH AAH F0H AAH 2AAAH 55H 5555H F0H T10.5 504 2nd1 Write Cycle Addr2 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 55H 55H 55H 55H 55H 3rd1 Write Cycle 5555H 5555H 5555H 5555H 5555H A0H 80H 80H 80H 90H 4th1 Write Cycle Data Data AAH AAH AAH BA3 5555H 5555H 5555H 5th1 Write Cycle Addr2 2AAAH 2AAAH 2AAAH 6th1 Write Cycle Data 30H 50H 10H Data Addr2 Data Addr2 Data Addr2 55H 55H 55H SAX4 BAX 5 5555H 1. FWH Mode uses consecutive Write cycles to complete a command sequence; PP Mode uses consecutive bus cycles to complete a command sequence. 2. Address format A14-A0 (Hex), Addresses A15-A21 can be VIL or VIH, but no other value, for the Command sequence in PP Mode. 3. BA = Program Byte address 4. SAX for Sector-Erase Address 5. BAX for Block-Erase Address 6. Chip-Erase is supported in PP Mode only 7. SST Manufacturer's ID = BFH, is read with A0=0, With A17-A1 = 0; 49LF002A Device ID = 57H, is read with A0 = 1. With A18-A = 0; 49LF003A Device ID = 1BH, is read with A0 = 1. With A18-A1 = 0; 49LF004A Device ID = 60H, is read with A0 = 1. With A19-A1 = 0; 49LF008A Device ID = 5AH, is read with A0 = 1. 8. The device does not remain in Software Product ID mode if powered down. 9. Both Software ID Exit operations are equivalent (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 18 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (Ta=25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Do not violate processor or chipset limitations on the INIT# pin. 2. Outputs shorted for no more than one second. No more than one output shorted at a time. This note applies to non-PCI outputs. OPERATING RANGE Range Commercial Ambient Temp 0C to +85C VDD 3.0-3.6V AC CONDITIONS OF TEST1 Input Rise/Fall Time . . . . . . . . . . . . . . . 3 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 24 and 25 1. FWH interface signals use PCI load test conditions TABLE 11: DC OPERATING CHARACTERISTICS (ALL INTERFACE) Limits Symbol IDD Parameter Power Supply Current Read Write ISB IRY1 II ILI ILO VIHI2 VILI2 VIL Standby VDD Current (FWH Interface) Ready Mode VDD Current (FWH Interface) Input Current for IC, ID [3:0] pins Input Leakage Current Output Leakage Current INIT# Input High Voltage INIT# Input Low Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 0.9 VDD 1.0 -0.5 -0.5 0.5 VDD 12 24 100 10 200 1 1 VDD+0.5 0.4 0.3 VDD VDD+0.5 0.1 VDD mA mA A mA A A A V V V V V V Min Max Units Test Conditions Address input=VIL/VIH, at F=1/TRC Min, VDD=VDD Max (PP Mode) OE#=VIH, WE#=VIH OE#=VIH, WE#=VIL, VDD=VDD Max (PP Mode) FWH4=0.9VDD, f=33 MHz VDD=VDD Max, All other inputs 0.9 VDD or 0.1 VDD FWH4=VIL, f=33 MHz VDD=VDD Max All other inputs 0.9 VDD or 0.1 VDD VIN=GND to VDD, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Max VDD=VDD Min VDD=VDD Min VDD=VDD Max IOL=1500A, VDD=VDD Min IOH=-500 A, VDD=VDD Min T11.8 504 VIH VOL VOH 1. The device is in Ready Mode when no activity is on the FWH bus. 2. Do not violate processor or chipset specification regarding INIT# voltage. (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 19 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information TABLE 12: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol TPU-READ1 TPU-WRITE 1 www..com Parameter Power-up to Read Operation Power-up to Write Operation Minimum 100 100 Units s s T12.2 504 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter TABLE 13: PIN IMPEDANCE Parameter CI/O 1 (VDD=3.3V, Ta=25 C, f=1 Mhz, other pins open) Description I/O Pin Capacitance Input Capacitance Pin Inductance Test Condition VI/O = 0V VIN = 0V Maximum 12 pF 12 pF 20 nH T13.4 504 CIN1 LPIN2 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. Refer to PCI spec. TABLE 14: RELIABILITY CHARACTERISTICS Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78 T14.3 504 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 15: CLOCK TIMING PARAMETERS Symbol TCYC THIGH TLOW Parameter CLK Cycle Time CLK High Time CLK Low Time CLK Slew Rate (peak-to-peak) RST# or INIT# Slew Rate Min 30 11 11 1 50 4 Max Units ns ns ns V/ns mV/ns T15.1 504 Tcyc Thigh 0.6 VDD 0.5 VDD 0.4 VDD 0.3 VDD 0.2 VDD 504 ILL F27.0 Tlow 0.4 VDD p-to-p (minimum) FIGURE 9: CLK WAVEFORM (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 20 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com AC CHARACTERISTICS (FWH MODE) TABLE 16: READ/WRITE CYCLE TIMING PARAMETERS (FWH MODE), VDD =3.0-3.6V Symbol TCYC TSU TDH TVAL1 TBP TSE TBE TSCE TON TOFF Parameter Clock Cycle Time Data Set Up Time to Clock Rising Clock Rising to Data Hold Time Clock Rising to Data Valid Byte Programming Time Sector-Erase Time Block-Erase Time Chip-Erase Time Clock Rising to Active (Float to Active Delay) Clock Rising to Inactive (Active to Float Delay) 2 28 Min 30 7 0 2 11 20 25 25 100 Max Units ns ns ns ns s ms ms ms ns ns T16.3 504 1. Minimum and maximum times have different loads. See PCI spec. TABLE 17: AC INPUT/OUTPUT SPECIFICATIONS (FWH MODE) Symbol IOH(AC) Parameter Switching Current High Min -12 VDD -17.1(VDD-VOUT) Equation C1 (Test Point) IOL(AC) Switching Current Low 16 VDD 26.7 VOUT -32 VDD Equation D1 mA mA mA mA mA mA 4 4 V/ns V/ns Max Units mA mA Conditions 0 < VOUT 0.3VDD 0.3VDD < VOUT < 0.9VDD 0.7VDD < VOUT T17.3 504 (Test Point) ICL ICH slewr2 slewf2 Low Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate -25+(VIN+1)/0.015 25+(VIN-VDD-1)/0.015 1 1 38 VDD 1. See PCI spec. 2. PCI specification output load is used. TABLE 18: RESET TIMING PARAMETERS, VDD =3.0-3.6V (FWH MODE) Symbol TPRST TKRST TRSTP TRSTF TRST1 TRSTE Parameter VDD stable to Reset Low Clock Stable to Reset Low RST# Pulse Width RST# Low to Output Float RST# High to FWH4 Low RST# Low to reset during Sector-/Block-Erase or Program 1 10 Min 1 100 100 48 Max Units ms s ns ns s s T18.5 504 1. There will be a latency of TRSTE if a reset procedure is performed during a Program or Erase operation. (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 21 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com VDD CLK TPRST TKRST RST#/INIT# TRSTP TRSTE TRSTF TRST Sector-/Block-Erase or Program operation aborted FWH[3:0] FWH4 504 ILL F51.1 FIGURE 10: RESET TIMING DIAGRAM VTH CLK VTEST VTL TVAL FWH [3:0] (Valid Output Data) FWH [3:0] (Float Output Data) TON TOFF 504 ILL F49.1 FIGURE 11: OUTPUT TIMING PARAMETERS (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 22 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com VTH CLK TSU VTEST VTL TDH FWH [3:0] (Valid Input Data) Inputs Valid VMAX 504 ILL F50.1 FIGURE 12: INPUT TIMING PARAMETERS TABLE 19: INTERFACE MEASUREMENT CONDITION PARAMETERS Symbol VTH1 VTL 1 Value 0.6 VDD 0.2 VDD 0.4 VDD 0.4 VDD 1 V/ns Units V V V V T19.3 504 VTEST VMAX 1 Input Signal Edge Rate 1. The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met with no more overdrive than this. VMAX specified the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use different voltage values, but must correlate results back to these parameters. (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 23 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com AC CHARACTERISTICS (PP MODE) TABLE 20: READ CYCLE TIMING PARAMETERS VDD =3.0-3.6V (PP MODE) Symbol TRC TRST TAS TAH TAA TOE TOLZ TOHZ TOH Parameter Read Cycle Time RST# High to Row Address Setup R/C# Address Set-up Time R/C# Address Hold Time Address Access Time Output Enable Access Time OE# Low to Active Output OE# High to High-Z Output Output Hold from Address Change 0 0 35 Min 270 1 45 45 120 60 Max Units ns s ns ns ns ns ns ns ns T20.2 504 TABLE 21: PROGRAM/ERASE CYCLE TIMING PARAMETERS VDD =3.0-3.6V (PP MODE) Symbol TRST TAS TAH TCWH TOES TOEH TOEP TOET TWP TWPH TDS TDH TIDA TBP TSE TBE TSCE Parameter RST# High to Row Address Setup R/C# Address Setup Time R/C# Address Hold Time R/C# to Write Enable High Time OE# High Setup Time OE# High Hold Time OE# to Data# Polling Delay OE# to Toggle Bit Delay WE# Pulse Width WE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Byte Programming Time Sector-Erase Time Block-Erase Time Chip-Erase Time 100 100 50 5 150 20 25 25 100 Min 1 50 50 50 20 20 40 40 Max Units s ns ns ns ns ns ns ns ns ns ns ns ns s ms ms ms T21.2 504 TABLE 22: RESET TIMING PARAMETERS, VDD =3.0-3.6V (PP MODE) Symbol TPRST TRSTP TRSTF TRST1 TRSTE TRSTC Parameter VDD stable to Reset Low RST# Pulse Width RST# Low to Output Float RST# High to Row Address Setup RST# Low to reset during Sector-/Block-Erase or Program RST# Low to reset during Chip-Erase 1 10 50 Min 1 100 48 Max Units ms ns ns s s s T22.1 504 1. There will be a reset latency of TRSTE or TRSTC if a reset procedure is performed during a Program or Erase operation. (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 24 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com VDD TPRST Addresses Row Address R/C# RST# TRSTP TRSTE Sector-/Block-Erase or Program operation aborted Chip-Erase aborted TRSTC TRSTF TRST DQ7-0 504 ILL F58.0 FIGURE 13: RESET TIMING DIAGRAM RST# TRSTP TRST TRC Row Address TAS TAH Column Address TAS TAH Row Address Column Address Addresses R/C# WE# OE# TOE TOLZ VIH TAA TOH TOHZ Data Valid High-Z 504 ILL F28.2 DQ7-0 High-Z FIGURE 14: READ CYCLE TIMING DIAGRAM (PP MODE) (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 25 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com TRSTP RST# Addresses TRST Row Address TAS TAH Column Address TAS TAH R/C# TCWH TOEH OE# WE# TOES TWP TWPH TDH TDS DQ7-0 Data Valid 504 ILL F29.1 FIGURE 15: WRITE CYCLE TIMING DIAGRAM (PP MODE) Addresses Row Column R/C# WE# OE# TOEP DQ7 D D# D# D 504 ILL F54.2 FIGURE 16: DATA# POLLING TIMING DIAGRAM (PP MODE) (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 26 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com Addresses Row Column R/C# WE# OE# TOET DQ6 D D 504 ILL F55.0 FIGURE 17: TOGGLE BIT TIMING DIAGRAM (PP MODE) Four-Byte Code for Byte-Program Addresses 5555 R/C# 2AAA 5555 BA OE# TWP TBP TWPH WE# SB0 SB1 SB2 SB3 Internal Program Starts DQ7-0 AA 55 A0 Data BA = Byte-Program Address 504 ILL F53.0 FIGURE 18: BYTE-PROGRAM TIMING DIAGRAM (PP MODE) (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 27 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com Six-Byte code for Sector-Erase Operation Addresses 5555 R/C# 2AAA 5555 5555 2AAA SAx OE# TWP TSE TWPH WE# SB0 DQ7-0 AA SB1 55 SB2 80 SB3 AA SB4 55 SB5 30 Internal Erasure Starts SAx = Sector Address 504 ILL F32.1 FIGURE 19: SECTOR-ERASE TIMING DIAGRAM (PP MODE) Six-Byte code for Block-Erase Operation Addresses 5555 R/C# 2AAA 5555 5555 2AAA BAx OE# TWP TBE TWPH WE# SB0 DQ7-0 AA SB1 55 SB2 80 SB3 AA SB4 55 SB5 50 Internal Erasure Starts BAx = Block Address 504 ILL F48.1 FIGURE 20: BLOCK-ERASE TIMING DIAGRAM (PP MODE) (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 28 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com Six-Byte code for Chip-Erase Operation Addresses 5555 R/C# 2AAA 5555 5555 2AAA 5555 OE# TWP TSCE TWPH WE# SB0 DQ7-0 AA SB1 55 SB2 80 SB3 AA SB4 55 SB5 10 Internal Erasure Starts 504 ILL F33.1 FIGURE 21: CHIP-ERASE TIMING DIAGRAM (PP MODE) Three-byte sequence for Software ID Entry Addresses 5555 2AAA 5555 0000 0001 R/C# OE# TWP WE# TWPH DQ7-0 AA SW0 55 SW1 90 SW2 504 ILL F34.4 TIDA TAA BF Device ID Device ID = 57H for SST49LF002A, 1BH for SST49LF003A, 60H for SST49LF004A, 5AH for SST49LF008A FIGURE 22: SOFTWARE ID ENTRY AND READ (PP MODE) (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 29 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com Three-Byte Sequence for Software ID Exit and Reset Addresses 5555 R/C# 2AAA 5555 TIDA OE# TWP WE# T WHP SW0 DQ7-0 AA SW1 55 SW2 F0 504 ILL F35.1 FIGURE 23: SOFTWARE ID EXIT AND RESET (PP MODE) VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 504 ILL F06.1 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 24: AC INPUT/OUTPUT REFERENCE WAVEFORMS (PP MODE) TO TESTER TO DUT CL 504 ILL F07.0 FIGURE 25: A TEST LOAD EXAMPLE (PP MODE) (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 30 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com Start Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 504 ILL F36.1 FIGURE 26: BYTE-PROGRAM ALGORITHM (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 31 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com Internal Timer ByteProgram/Erase Initiated Toggle Bit ByteProgram/Erase Initiated Data# Polling ByteProgram/Erase Initiated Wait TBP, TSCE, TBE or TSE Read byte Read DQ7 Program/Erase Completed Read same byte No Is DQ7 = true data? Yes No Does DQ6 match? Yes Program/Erase Completed Program/Erase Completed 504 ILL F37.0 FIGURE 27: WAIT OPTIONS (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 32 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com Software Product ID Entry Command Sequence Software Product ID Exit & Reset Command Sequence Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: F0H Address: XXH Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Wait TIDA Write data: 90H Address: 5555H Write data: F0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation 504 ILL F38.1 FIGURE 28: SOFTWARE PRODUCT COMMAND FLOWCHARTS (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 33 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com Chip-Erase Command Sequence Write data: AAH Address: 5555H Block-Erase Command Sequence Write data: AAH Address: 5555H Sector-Erase Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: 80H Address: 5555H Write data: 80H Address: 5555H Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 10H Address: 5555H Write data: 50H Address: BAX Write data: 30H Address: SAX Wait Options Wait Options Wait Options Chip erased to FFH Block erased to FFH Sector erased to FFH 504 ILL F39.1 FIGURE 29: ERASE COMMAND SEQUENCE (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 34 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com PRODUCT ORDERING INFORMATION Device Speed Suffix1 XX Suffix2 XX Package Modifier H = 32 leads Package Type N = PLCC W = TSOP (type 1, die up, 8mm x 14mm) Operating Temperature C = Commercial = 0C to +85C Minimum Endurance 4 = 10,000 cycles Serial Access Clock Frequency 33 = 33 MHz Version Device Density 008 = 8 Mbit 004 = 4 Mbit 003 = 3 Mbit 002 = 2 Mbit Voltage Range L = 3.0-3.6V Device Family SST49LF00xA - XXX Valid combinations for SST49LF002A SST49LF002A-33-4C-WH SST49LF002A-33-4C-NH Valid combinations for SST49LF003A SST49LF003A-33-4C-WH SST49LF003A-33-4C-NH Valid combinations for SST49LF004A SST49LF004A-33-4C-WH SST49LF004A-33-4C-NH Valid combinations for SST49LF008A SST49LF008A-33-4C-WH Note: SST49LF008A-33-4C-NH Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 35 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A Advance Information www..com PACKAGING DIAGRAMS TOP VIEW .495 .485 .453 .447 .048 .042 2 1 32 SIDE VIEW .112 .106 .020 R. MAX. .029 x 30 .023 .040 R. .030 BOTTOM VIEW Optional Pin #1 Identifier .042 .048 .595 .585 .553 .547 .032 .026 .021 .013 .400 BSC .530 .490 .050 BSC .015 Min. .050 BSC .140 .125 .095 .075 .032 .026 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils. 32-plcc-NH-ILL.2 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 12.50 12.30 DETAIL 0.15 0.05 1.20 max. 0.70 0.50 14.20 13.80 0- 5 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 1mm 3. Coplanarity: 0.1 (.05) mm. 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 32-tsop-WH-ILL.6 0.70 0.50 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: WH X 14MM Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com (c)2001 Silicon Storage Technology, Inc. S71161-06-000 9/01 504 36 |
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